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1 Ergebnisse
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Characterization technique to implement self-timed cells fo..:
, In:
2014 11th International Conference on Electrical Engineering, Computing Science and Automatic Control (CCE)
,
Cisneros, Susana Ortega
;
Raygoza Panduro, Juan Jose
;
Reyes Baron, Jose Roberto
.. - p. 1-6 , 2014
Link:
https://doi.org/10.1109/ICEEE.2014.6978288
RT T1
2014 11th International Conference on Electrical Engineering, Computing Science and Automatic Control (CCE)
: T1
Characterization technique to implement self-timed cells for VLSI design blocks
UL https://suche.suub.uni-bremen.de/peid=ieee-6978288&Exemplar=1&LAN=DE A1 Cisneros, Susana Ortega A1 Raygoza Panduro, Juan Jose A1 Reyes Baron, Jose Roberto A1 Daniel Tonali Aranda, B. A1 Casillas, Z. Antonio YR 2014 K1 Libraries K1 Delays K1 Standards K1 Layout K1 Logic gates K1 Manufacturing K1 Integrated circuits K1 Self-timed K1 Standard cell K1 Alliance Tools SP 1 OP 6 LK http://dx.doi.org/https://doi.org/10.1109/ICEEE.2014.6978288 DO https://doi.org/10.1109/ICEEE.2014.6978288 SF ELIB - SuUB Bremen
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