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Gate-drain capacitance behaviour of the DMOS power transist..:
, In:
PESC 98 Record. 29th Annual IEEE Power Electronics Specialists Conference (Cat. No.98CH36196)
,
Deml, C.
;
Hoffmann, K.
- p. 1716,1717,1718,1719 , 1998
Link:
https://doi.org/10.1109/PESC.1998.703412
RT T1
PESC 98 Record. 29th Annual IEEE Power Electronics Specialists Conference (Cat. No.98CH36196)
: T1
Gate-drain capacitance behaviour of the DMOS power transistor under high current flow
UL https://suche.suub.uni-bremen.de/peid=ieee-703412&Exemplar=1&LAN=DE A1 Deml, C. A1 Hoffmann, K. YR 1998 SN 0275-9306 K1 Power transistors K1 Capacitance measurement K1 Current measurement K1 Voltage K1 Fluid flow measurement K1 Circuits K1 Equations K1 Power measurement K1 Capacitance-voltage characteristics K1 Thermal loading SP 1716,1717,1718,1719 LK http://dx.doi.org/https://doi.org/10.1109/PESC.1998.703412 DO https://doi.org/10.1109/PESC.1998.703412 SF ELIB - SuUB Bremen
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