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VLSI architecture design and implementation of a LDPC encod..:
, In:
2015 25th International Workshop on Power and Timing Modeling, Optimization and Simulation (PATMOS)
,
Alves Ferreira Neto, Nelson
;
de Oliveira, Joaquim Ranyere S.
;
de Oliveira, Wagner Luiz A.
. - p. 71-76 , 2015
Link:
https://doi.org/10.1109/PATMOS.2015.7347589
RT T1
2015 25th International Workshop on Power and Timing Modeling, Optimization and Simulation (PATMOS)
: T1
VLSI architecture design and implementation of a LDPC encoder for the IEEE 802.22 WRAN standard
UL https://suche.suub.uni-bremen.de/peid=ieee-7347589&Exemplar=1&LAN=DE A1 Alves Ferreira Neto, Nelson A1 de Oliveira, Joaquim Ranyere S. A1 de Oliveira, Wagner Luiz A. A1 Bittencourt, Joao Carlos N. YR 2015 K1 Registers K1 Inverters K1 Standards K1 Parity check codes K1 Coprocessors K1 LDPC K1 encoder K1 channel coding K1 802.22 K1 WRAN SP 71 OP 76 LK http://dx.doi.org/https://doi.org/10.1109/PATMOS.2015.7347589 DO https://doi.org/10.1109/PATMOS.2015.7347589 SF ELIB - SuUB Bremen
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