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FPGA hardware architecture with parallel data processing to..:
, In:
2015 CHILEAN Conference on Electrical, Electronics Engineering, Information and Communication Technologies (CHILECON)
,
Rodrigues, Ingrid Nunes
;
Silva de Melo, Charles Luiz
;
Mello da Frota Botinelly, Vanessa
. - p. 841-846 , 2015
Link:
https://doi.org/10.1109/Chilecon.2015.7404670
RT T1
2015 CHILEAN Conference on Electrical, Electronics Engineering, Information and Communication Technologies (CHILECON)
: T1
FPGA hardware architecture with parallel data processing to detect moving objects using the background image subtraction technique
UL https://suche.suub.uni-bremen.de/peid=ieee-7404670&Exemplar=1&LAN=DE A1 Rodrigues, Ingrid Nunes A1 Silva de Melo, Charles Luiz A1 Mello da Frota Botinelly, Vanessa A1 de Oliveira, Jozias Parente YR 2015 K1 Field programmable gate arrays K1 Image color analysis K1 Image segmentation K1 Hardware K1 Streaming media K1 Real-time systems K1 Hardware design languages K1 Digital Image Processing K1 background subtraction K1 FPGA SP 841 OP 846 LK http://dx.doi.org/https://doi.org/10.1109/Chilecon.2015.7404670 DO https://doi.org/10.1109/Chilecon.2015.7404670 SF ELIB - SuUB Bremen
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