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A 12b 180MS/s 0.068mm2 pipelined-SAR ADC with merged-residu..:
, In:
ESSCIRC Conference 2016: 42nd European Solid-State Circuits Conference
,
Zhong, Jianyu
;
Zhu, Yan
;
Chan, Chi-Hang
... - p. 169-172 , 2016
Link:
https://doi.org/10.1109/ESSCIRC.2016.7598269
RT T1 <cTitle>ESSCIRC Conference 2016: 42nd European Solid-State Circuits Conference</cTitle>: T1 <Title>A 12b 180MS/s 0.068mm2 pipelined-SAR ADC with merged-residue DAC for noise reduction</Title> UL https://suche.suub.uni-bremen.de/peid=ieee-7598269&Exemplar=1&LAN=DE A1 Zhong, Jianyu A1 Zhu, Yan A1 Chan, Chi-Hang A1 Sin, Sai-Weng A1 Seng-Pan, U. A1 Martins, R.P. YR 2016 K1 Switches K1 Timing K1 Calibration K1 Capacitance K1 Semiconductor device measurement K1 Prototypes K1 Clocks SP 169 OP 172 LK http://dx.doi.org/https://doi.org/10.1109/ESSCIRC.2016.7598269 DO https://doi.org/10.1109/ESSCIRC.2016.7598269 SF ELIB - SuUB Bremen
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