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1 Ergebnisse
1
A High Speed Clamped-Bit-Line Sensing Scheme For 1T Dynamic..:
, In:
1991 Symposium on VLSI Circuits
,
Blalock, T.N.
;
Jaeger, R.C.
- p. 61,62 , 1991
Link:
https://doi.org/10.1109/VLSIC.1991.760078
RT T1
1991 Symposium on VLSI Circuits
: T1
A High Speed Clamped-Bit-Line Sensing Scheme For 1T Dynamic RAMs
UL https://suche.suub.uni-bremen.de/peid=ieee-760078&Exemplar=1&LAN=DE A1 Blalock, T.N. A1 Jaeger, R.C. YR 1991 K1 Capacitance K1 Voltage K1 Impedance K1 Power supplies K1 Read-write memory K1 Circuit noise K1 Coupling circuits K1 Clamps K1 Random access memory K1 Circuit testing SP 61,62 LK http://dx.doi.org/https://doi.org/10.1109/VLSIC.1991.760078 DO https://doi.org/10.1109/VLSIC.1991.760078 SF ELIB - SuUB Bremen
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