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1 Ergebnisse
1
Novel Low Cost and Double Node Upset Tolerant Latch Design ..:
, In:
2016 IEEE 25th Asian Test Symposium (ATS)
,
Yan, Aibin
;
Huang, Zhengfeng
;
Fang, Xiangsheng
.. - p. 252-256 , 2016
Link:
https://doi.org/10.1109/ATS.2016.17
RT T1
2016 IEEE 25th Asian Test Symposium (ATS)
: T1
Novel Low Cost and Double Node Upset Tolerant Latch Design for Nanoscale CMOS Technology
UL https://suche.suub.uni-bremen.de/peid=ieee-7796122&Exemplar=1&LAN=DE A1 Yan, Aibin A1 Huang, Zhengfeng A1 Fang, Xiangsheng A1 Xu, Xiaolin A1 Liang, Huaguo YR 2016 SN 2377-5386 K1 Single node upset K1 double node upset K1 soft error K1 radiation hardening K1 latch design SP 252 OP 256 LK http://dx.doi.org/https://doi.org/10.1109/ATS.2016.17 DO https://doi.org/10.1109/ATS.2016.17 SF ELIB - SuUB Bremen
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