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1 Ergebnisse
1
Challenges and opportunities of vertical FET devices using ..:
, In:
2016 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S)
,
Veloso, A.
;
Tao, Z.
;
Li, W.
... - p. 1-3 , 2016
Link:
https://doi.org/10.1109/S3S.2016.7804409
RT T1 <cTitle>2016 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S)</cTitle>: T1 <Title>Challenges and opportunities of vertical FET devices using 3D circuit design layouts</Title> UL https://suche.suub.uni-bremen.de/peid=ieee-7804409&Exemplar=1&LAN=DE A1 Veloso, A. A1 Tao, Z. A1 Li, W. A1 Altamirano-Sanchez, E. A1 Versluijs, J. J. A1 Brus, S. A1 Matagne, P. A1 Waldron, N. A1 Ryckaert, J. A1 Mocuta, D. A1 Collaert, N. A1 Huynh-Bao, T. A1 Rosseel, E. A1 Paraschiv, V. A1 Devriendt, K. A1 Vecchio, E. A1 Delvaux, C. A1 Chan, B. T. A1 Ercken, M. YR 2016 K1 Doping K1 Random access memory K1 Logic gates K1 Wires K1 Transistors K1 Silicon K1 Electrodes K1 Vertical nanowire FETs K1 SRAM K1 CMOS scaling SP 1 OP 3 LK http://dx.doi.org/https://doi.org/10.1109/S3S.2016.7804409 DO https://doi.org/10.1109/S3S.2016.7804409 SF ELIB - SuUB Bremen
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