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A novel design and implementation of multi-valued logic ari..:
, In:
2016 IEEE International Conference on Recent Trends in Electronics, Information & Communication Technology (RTEICT)
,
Phanindra, L.S.
;
Rajath, M.N.
;
Rakesh, V.
. - p. 563-568 , 2016
Link:
https://doi.org/10.1109/RTEICT.2016.7807885
RT T1 <cTitle>2016 IEEE International Conference on Recent Trends in Electronics, Information & Communication Technology (RTEICT)</cTitle>: T1 <Title>A novel design and implementation of multi-valued logic arithmetic full adder circuit using CNTFET</Title> UL https://suche.suub.uni-bremen.de/peid=ieee-7807885&Exemplar=1&LAN=DE A1 Phanindra, L.S. A1 Rajath, M.N. A1 Rakesh, V. A1 Patel, K.S. Vasundara YR 2016 K1 CNTFETs K1 Logic gates K1 Adders K1 Threshold voltage K1 Inverters K1 Multivalued logic K1 Carbon Nanotube Field Effect Transistors (CNFETs) K1 SPICE Modelling K1 Ternary NAND K1 Ternary NOR K1 Ternary Full Adder SP 563 OP 568 LK http://dx.doi.org/https://doi.org/10.1109/RTEICT.2016.7807885 DO https://doi.org/10.1109/RTEICT.2016.7807885 SF ELIB - SuUB Bremen
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