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3.4 A 10nm FinFET 2.8GHz tri-gear deca-core CPU complex wit..:

, In: 2017 IEEE International Solid-State Circuits Conference (ISSCC),

Mair, Hugh ; Lin, Gordon ; Thippana, Achuta... - p. 56-57 , 2017

Link: https://doi.org/10.1109/ISSCC.2017.7870258

RT 
T1 <cTitle>2017 IEEE International Solid-State Circuits Conference (ISSCC)</cTitle>: T1 <Title>3.4 A 10nm FinFET 2.8GHz tri-gear deca-core CPU complex with optimized power-delivery network for mobile SoC performance</Title>

UL https://suche.suub.uni-bremen.de/peid=ieee-7870258&Exemplar=1&LAN=DE
				
A1 Mair, Hugh
A1 Lin, Gordon
A1 Thippana, Achuta
A1 Li, Kent
A1 Rahman, Manzur
A1 Kuo, Wuan
A1 Yen, David
A1 Zhuang, Yi-Chang
A1 Fu, Ue
A1 Wang, Hung-Wei
A1 Peng, Mark
A1 Wang, Ericbill
A1 Wu, Cheng-Yuh
A1 Dosluoglu, Taner
A1 Gelman, Anatoly
A1 Dia, Daniel
A1 Gurumurthy, Girishankar
A1 Hsieh, Tony
A1 Lin, W.X.
A1 Tzeng, Ray
A1 Wu, Jengding
A1 Wang, C.H.
A1 Wang, Alice
A1 Ko, Uming
A1 Kao, Ping
A1 Tsai, Yuwen
A1 Gururajarao, Sumanth
A1 Lagerquist, Rolf
A1 Son, Jin
A1 Gammie, Gordon
YR 2017
SN 2376-8606
K1 Monitoring
K1 Voltage measurement
K1 Software
K1 Transistors
K1 Central Processing Unit
K1 Clocks
K1 Current measurement
SP 56
OP 57
LK http://dx.doi.org/https://doi.org/10.1109/ISSCC.2017.7870258
DO https://doi.org/10.1109/ISSCC.2017.7870258
SF ELIB - SuUB Bremen

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