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Exploiting parallelism for faster implementation of Bubble ..:
, In:
2016 2nd International Conference on Electrical, Computer & Telecommunication Engineering (ICECTE)
,
Lipu, Ashrak Rahman
;
Amin, Ruhul
;
Islam Mondal, Md. Nazrul
. - p. 1-4 , 2016
Link:
https://doi.org/10.1109/ICECTE.2016.7879576
RT T1
2016 2nd International Conference on Electrical, Computer & Telecommunication Engineering (ICECTE)
: T1
Exploiting parallelism for faster implementation of Bubble sort algorithm using FPGA
UL https://suche.suub.uni-bremen.de/peid=ieee-7879576&Exemplar=1&LAN=DE A1 Lipu, Ashrak Rahman A1 Amin, Ruhul A1 Islam Mondal, Md. Nazrul A1 Mamun, Md. Al YR 2016 K1 Field programmable gate arrays K1 Clocks K1 Sorting K1 Parallel processing K1 Algorithm design and analysis K1 Computers K1 Wiring K1 FPGA K1 Bubble Sort K1 Clock Cycle K1 Odd-even transposition K1 Swappers K1 Schematic view SP 1 OP 4 LK http://dx.doi.org/https://doi.org/10.1109/ICECTE.2016.7879576 DO https://doi.org/10.1109/ICECTE.2016.7879576 SF ELIB - SuUB Bremen
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