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1 Ergebnisse
1
Defect Analysis and Cost-Effective Resilience Architecture ..:
, In:
2017 IEEE International Symposium on High Performance Computer Architecture (HPCA)
,
Cha, Sanguhn
;
Seongil, O.
;
Shin, Hyunsung
... - p. 61-72 , 2017
Link:
https://doi.org/10.1109/HPCA.2017.30
RT T1
2017 IEEE International Symposium on High Performance Computer Architecture (HPCA)
: T1
Defect Analysis and Cost-Effective Resilience Architecture for Future DRAM Devices
UL https://suche.suub.uni-bremen.de/peid=ieee-7920814&Exemplar=1&LAN=DE A1 Cha, Sanguhn A1 Seongil, O. A1 Shin, Hyunsung A1 Hwang, Sangjoon A1 Park, Kwangil A1 Jang, Seong Jin A1 Choi, Joo Sun A1 Jin, Gyo Young A1 Son, Young Hoon A1 Cho, Hyunyoon A1 Ahn, Jung Ho A1 Kim, Nam Sung YR 2017 SN 2378-203X K1 Random access memory K1 Circuit faults K1 Error correction codes K1 Capacitors K1 Capacitance K1 Performance evaluation K1 Transistors K1 DRAM K1 resilience K1 In-DRAM ECC K1 single-cell faults K1 long-burst writes SP 61 OP 72 LK http://dx.doi.org/https://doi.org/10.1109/HPCA.2017.30 DO https://doi.org/10.1109/HPCA.2017.30 SF ELIB - SuUB Bremen
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