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1
Design of 5-Bit Flash ADC Using Multiple Input Standard Cel..:
, In:
2017 IEEE Computer Society Annual Symposium on VLSI (ISVLSI)
,
Khalapure, Sumit
;
R.K., Siddharth
;
Y.B., Nithin Kumar
. - p. 585-588 , 2017
Link:
https://doi.org/10.1109/ISVLSI.2017.108
RT T1
2017 IEEE Computer Society Annual Symposium on VLSI (ISVLSI)
: T1
Design of 5-Bit Flash ADC Using Multiple Input Standard Cell Gates for Large Input Swing
UL https://suche.suub.uni-bremen.de/peid=ieee-7987584&Exemplar=1&LAN=DE A1 Khalapure, Sumit A1 R.K., Siddharth A1 Y.B., Nithin Kumar A1 M.H., Vasantha YR 2017 SN 2159-3477 K1 Logic gates K1 Computer architecture K1 Standards K1 Switches K1 Microprocessors K1 Threshold voltage K1 Dynamic range K1 Analog to digital converters K1 automated synthesis K1 threshold inverter quantization K1 multiplication factor K1 standard cell K1 switching threshold SP 585 OP 588 LK http://dx.doi.org/https://doi.org/10.1109/ISVLSI.2017.108 DO https://doi.org/10.1109/ISVLSI.2017.108 SF ELIB - SuUB Bremen
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