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1 Ergebnisse
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Low-trigger ESD protection design with latch-up immunity fo..:
, In:
2017 IEEE 24th International Symposium on the Physical and Failure Analysis of Integrated Circuits (IPFA)
,
Chiang, Chun
;
Chang, Ping-Chen
;
Chao, Mei-Ling
... - p. 1-3 , 2017
Link:
https://doi.org/10.1109/IPFA.2017.8060226
RT T1
2017 IEEE 24th International Symposium on the Physical and Failure Analysis of Integrated Circuits (IPFA)
: T1
Low-trigger ESD protection design with latch-up immunity for 5-V CMOS application by drain engineering
UL https://suche.suub.uni-bremen.de/peid=ieee-8060226&Exemplar=1&LAN=DE A1 Chiang, Chun A1 Chang, Ping-Chen A1 Chao, Mei-Ling A1 Tang, Tien-Hao A1 Su, Kuan-Cheng A1 Ker, Ming-Dou YR 2017 SN 1946-1550 K1 Electrostatic discharges K1 Logic gates K1 Robustness K1 CMOS technology K1 Implants K1 Electron devices SP 1 OP 3 LK http://dx.doi.org/https://doi.org/10.1109/IPFA.2017.8060226 DO https://doi.org/10.1109/IPFA.2017.8060226 SF ELIB - SuUB Bremen
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