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1 Ergebnisse
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A 1.2 pJ/cycle KHz Timer Circuit for Heavily Duty-Cycled Sy..:
, In:
2018 31st International Conference on VLSI Design and 2018 17th International Conference on Embedded Systems (VLSID)
,
Manikandan, R.R.
;
Singhal, Vipul
;
Chauhan, Rajat
.. - p. 171-176 , 2018
Link:
https://doi.org/10.1109/VLSID.2018.57
RT T1 <cTitle>2018 31st International Conference on VLSI Design and 2018 17th International Conference on Embedded Systems (VLSID)</cTitle>: T1 <Title>A 1.2 pJ/cycle KHz Timer Circuit for Heavily Duty-Cycled Systems</Title> UL https://suche.suub.uni-bremen.de/peid=ieee-8326920&Exemplar=1&LAN=DE A1 Manikandan, R.R. A1 Singhal, Vipul A1 Chauhan, Rajat A1 Menezes, Vinod A1 Mehendale, Mahesh YR 2018 SN 2380-6923 K1 Oscillators K1 Delays K1 Current measurement K1 Voltage measurement K1 Transistors K1 Low-power electronics K1 Ultra low power K1 relaxation K1 subthreshold K1 dutycycle K1 ring oscillator K1 non-overlap K1 short circuit current K1 timing SP 171 OP 176 LK http://dx.doi.org/https://doi.org/10.1109/VLSID.2018.57 DO https://doi.org/10.1109/VLSID.2018.57 SF ELIB - SuUB Bremen
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