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1 Ergebnisse
1
7.1 An 11.5TOPS/W 1024-MAC Butterfly Structure Dual-Core Sp..:
, In:
2019 IEEE International Solid- State Circuits Conference - (ISSCC)
,
Song, Jinook
;
Cho, Yunkyo
;
Park, Jun-Seok
... - p. 130-132 , 2019
Link:
https://doi.org/10.1109/ISSCC.2019.8662476
RT T1
2019 IEEE International Solid- State Circuits Conference - (ISSCC)
: T1
7.1 An 11.5TOPS/W 1024-MAC Butterfly Structure Dual-Core Sparsity-Aware Neural Processing Unit in 8nm Flagship Mobile SoC
UL https://suche.suub.uni-bremen.de/peid=ieee-8662476&Exemplar=1&LAN=DE A1 Song, Jinook A1 Cho, Yunkyo A1 Park, Jun-Seok A1 Jang, Jun-Woo A1 Lee, Sehwan A1 Song, Joon-Ho A1 Lee, Jae-Gon A1 Kang, Inyup YR 2019 SN 2376-8606 K1 Parallel processing K1 Neural networks K1 Kernel K1 Semiconductor device measurement K1 Bandwidth K1 Central Processing Unit K1 Clocks SP 130 OP 132 LK http://dx.doi.org/https://doi.org/10.1109/ISSCC.2019.8662476 DO https://doi.org/10.1109/ISSCC.2019.8662476 SF ELIB - SuUB Bremen
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