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Capacitance and Surface Potential Model for III-V Double-Ga..:
, In:
2019 2nd International Symposium on Devices, Circuits and Systems (ISDCS)
,
Chandran, Sarath G.M.
;
Ganeriwala, Mohit D.
;
Mohapatra, Nihar Ranjan
- p. 1-5 , 2019
Link:
https://doi.org/10.1109/ISDCS.2019.8719281
RT T1
2019 2nd International Symposium on Devices, Circuits and Systems (ISDCS)
: T1
Capacitance and Surface Potential Model for III-V Double-Gate FET
UL https://suche.suub.uni-bremen.de/peid=ieee-8719281&Exemplar=1&LAN=DE A1 Chandran, Sarath G.M. A1 Ganeriwala, Mohit D. A1 Mohapatra, Nihar Ranjan YR 2019 K1 Mathematical model K1 Quantum capacitance K1 Logic gates K1 Semiconductor device modeling K1 Gallium arsenide K1 Insulators K1 modeling K1 DGFET K1 III-V K1 quantum capacitance K1 centroid capacitance SP 1 OP 5 LK http://dx.doi.org/https://doi.org/10.1109/ISDCS.2019.8719281 DO https://doi.org/10.1109/ISDCS.2019.8719281 SF ELIB - SuUB Bremen
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