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SAT Based Place-And-Route for High-Speed Designs on 2.5D FP..:
, In:
2018 International Conference on Field-Programmable Technology (FPT)
,
Ravishankar, Chirag
;
Fraisse, Henri
;
Gaitonde, Dinesh
- p. 118-125 , 2018
Link:
https://doi.org/10.1109/FPT.2018.00027
RT T1
2018 International Conference on Field-Programmable Technology (FPT)
: T1
SAT Based Place-And-Route for High-Speed Designs on 2.5D FPGAs
UL https://suche.suub.uni-bremen.de/peid=ieee-8742281&Exemplar=1&LAN=DE A1 Ravishankar, Chirag A1 Fraisse, Henri A1 Gaitonde, Dinesh YR 2018 K1 Clocks K1 Field programmable gate arrays K1 Delays K1 Routing K1 Performance evaluation K1 Stacking K1 FPGA K1 SSIT K1 2.5D ICs K1 SAT based PNR K1 Fixing Hold K1 Laguna K1 Xilinx K1 Inter SLR SP 118 OP 125 LK http://dx.doi.org/https://doi.org/10.1109/FPT.2018.00027 DO https://doi.org/10.1109/FPT.2018.00027 SF ELIB - SuUB Bremen
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