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Early Testable Addressable Logic (ETAL) Test Structure: Sho..:

, In: 2019 30th Annual SEMI Advanced Semiconductor Manufacturing Conference (ASMC),

Ahsan, Ishtiaq ; Khan, Shahrukh ; Winkler, Joerg... - p. 1-4 , 2019

Link: https://doi.org/10.1109/ASMC.2019.8791769

RT 
T1 <cTitle>2019 30th Annual SEMI Advanced Semiconductor Manufacturing Conference (ASMC)</cTitle>: T1 <Title>Early Testable Addressable Logic (ETAL) Test Structure: Showcasing the use of an Alternate Logic Yield Learning Test Structure for Technology Development</Title>

UL https://suche.suub.uni-bremen.de/peid=ieee-8791769&Exemplar=1&LAN=DE
				
A1 Ahsan, Ishtiaq
A1 Khan, Shahrukh
A1 Winkler, Joerg
A1 Sekar, Kannan
A1 Bawaskar, Neerja
A1 Crown, Steve
A1 Zhang, Kan
A1 O'tool, Martin
A1 Lin, Teng-Yin
A1 Lagus, Mark
A1 Sohn, D.K.
A1 Greenslit, Daniel
A1 Evans, Bill
A1 Laaksonen, Toni
A1 Gordon, Tarl
A1 Song, Zhigang
A1 Liu, Yandong
A1 Masnik, John
A1 Barth, Frank
YR 2019
SN 2376-6697
K1 Logic testing
K1 Failure analysis
K1 Random access memory
K1 Correlation
K1 Metals
K1 Arrays
K1 Software
K1 Yield Learning
K1 Logic Yield
K1 Defect
K1 Test-Structure
K1 Functional yield
SP 1
OP 4
LK http://dx.doi.org/https://doi.org/10.1109/ASMC.2019.8791769
DO https://doi.org/10.1109/ASMC.2019.8791769
SF ELIB - SuUB Bremen

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