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1 Ergebnisse
1
A Delay-Aware Implementation Scheme for Cost-Effective Impl..:
, In:
2019 IEEE International Test Conference in Asia (ITC-Asia)
,
Hsieh, Tong-Yu
;
Lin, Kuang-Chun
;
Lin, Hsin-Hsien
- p. 145-150 , 2019
Link:
https://doi.org/10.1109/ITC-Asia.2019.00038
RT T1
2019 IEEE International Test Conference in Asia (ITC-Asia)
: T1
A Delay-Aware Implementation Scheme for Cost-Effective Implication-Based Concurrent Error Detection
UL https://suche.suub.uni-bremen.de/peid=ieee-8872096&Exemplar=1&LAN=DE A1 Hsieh, Tong-Yu A1 Lin, Kuang-Chun A1 Lin, Hsin-Hsien YR 2019 K1 Delays K1 Wires K1 Logic gates K1 Capacitance K1 Hardware K1 Logic circuits K1 Reliability K1 concurrent error detection, delay overhead, implications, implication reduction, probability of error detection SP 145 OP 150 LK http://dx.doi.org/https://doi.org/10.1109/ITC-Asia.2019.00038 DO https://doi.org/10.1109/ITC-Asia.2019.00038 SF ELIB - SuUB Bremen
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