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1 Ergebnisse
1
Quantum Logic Synthesis with Formal Verification:
, In:
2019 IEEE 62nd International Midwest Symposium on Circuits and Systems (MWSCAS)
,
Smith, Kaitlin N.
;
Thornton, Mitchell A.
- p. 73-76 , 2019
Link:
https://doi.org/10.1109/MWSCAS.2019.8885132
RT T1
2019 IEEE 62nd International Midwest Symposium on Circuits and Systems (MWSCAS)
: T1
Quantum Logic Synthesis with Formal Verification
UL https://suche.suub.uni-bremen.de/peid=ieee-8885132&Exemplar=1&LAN=DE A1 Smith, Kaitlin N. A1 Thornton, Mitchell A. YR 2019 SN 1558-3899 K1 Qubit K1 Logic gates K1 Tools K1 Benchmark testing K1 Cost function K1 quantum information processing K1 quantum computing K1 quantum logic synthesis K1 technology mapping SP 73 OP 76 LK http://dx.doi.org/https://doi.org/10.1109/MWSCAS.2019.8885132 DO https://doi.org/10.1109/MWSCAS.2019.8885132 SF ELIB - SuUB Bremen
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