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1 Ergebnisse
1
Netlist Optimization by Gate Merging:
, In:
2019 IFIP/IEEE 27th International Conference on Very Large Scale Integration (VLSI-SoC)
,
Oliveira Conceicao, Calebe Micael de
;
Reis, Ricardo Augusto da Luz
- p. 236-237 , 2019
Link:
https://doi.org/10.1109/VLSI-SoC.2019.8920291
RT T1
2019 IFIP/IEEE 27th International Conference on Very Large Scale Integration (VLSI-SoC)
: T1
Netlist Optimization by Gate Merging
UL https://suche.suub.uni-bremen.de/peid=ieee-8920291&Exemplar=1&LAN=DE A1 Oliveira Conceicao, Calebe Micael de A1 Reis, Ricardo Augusto da Luz YR 2019 SN 2324-8440 K1 Transistors K1 Logic gates K1 Libraries K1 Wires K1 Optimization K1 Tools K1 Measurement K1 Logic Synthesis K1 Physical Synthesis K1 SCCG K1 Layout Generator SP 236 OP 237 LK http://dx.doi.org/https://doi.org/10.1109/VLSI-SoC.2019.8920291 DO https://doi.org/10.1109/VLSI-SoC.2019.8920291 SF ELIB - SuUB Bremen
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