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A Simplified Layout-Level method for Single Event Transient..:
, In:
2019 IFIP/IEEE 27th International Conference on Very Large Scale Integration (VLSI-SoC)
,
Schvittz, Rafael
;
Franco, Denis Teixeira
;
Soares, Leomar
. - p. 185-190 , 2019
Link:
https://doi.org/10.1109/VLSI-SoC.2019.8920333
RT T1
2019 IFIP/IEEE 27th International Conference on Very Large Scale Integration (VLSI-SoC)
: T1
A Simplified Layout-Level method for Single Event Transient Faults Susceptibility on Logic Gates
UL https://suche.suub.uni-bremen.de/peid=ieee-8920333&Exemplar=1&LAN=DE A1 Schvittz, Rafael A1 Franco, Denis Teixeira A1 Soares, Leomar A1 Butzen, Paulo Francisco YR 2019 SN 2324-8440 K1 Logic gates K1 Integrated circuit reliability K1 Layout K1 Circuit faults K1 Single event transients K1 Probabilistic logic K1 reliability K1 single event effects K1 single event transient K1 failure rate SP 185 OP 190 LK http://dx.doi.org/https://doi.org/10.1109/VLSI-SoC.2019.8920333 DO https://doi.org/10.1109/VLSI-SoC.2019.8920333 SF ELIB - SuUB Bremen
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