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1 Ergebnisse
1
Exploring area and total wirelength using a cell merging te..:
, In:
2019 IFIP/IEEE 27th International Conference on Very Large Scale Integration (VLSI-SoC)
,
Albinagorta, Kevin A. Caceres
;
Conceicao, Calebe
;
Cardenas, Carlos Silva
. - p. 329-334 , 2019
Link:
https://doi.org/10.1109/VLSI-SoC.2019.8920337
RT T1
2019 IFIP/IEEE 27th International Conference on Very Large Scale Integration (VLSI-SoC)
: T1
Exploring area and total wirelength using a cell merging technique
UL https://suche.suub.uni-bremen.de/peid=ieee-8920337&Exemplar=1&LAN=DE A1 Albinagorta, Kevin A. Caceres A1 Conceicao, Calebe A1 Cardenas, Carlos Silva A1 Reis, Ricardo YR 2019 SN 2324-8440 K1 Transistors K1 Tools K1 Logic gates K1 Layout K1 Libraries K1 Computer architecture K1 Merging K1 Logic Synthesis K1 Physical Synthesis K1 SCCG K1 Layout Generator SP 329 OP 334 LK http://dx.doi.org/https://doi.org/10.1109/VLSI-SoC.2019.8920337 DO https://doi.org/10.1109/VLSI-SoC.2019.8920337 SF ELIB - SuUB Bremen
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