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1
Performance Analysis of Underlap Double Gate Oxide Stacked ..:
, In:
2019 TEQIP III Sponsored International Conference on Microwave Integrated Circuits, Photonics and Wireless Networks (IMICPW)
,
Bhattacharyya, Amit
;
Pachal, Prithviraj
;
Pradhan, Anirban
.. - p. 126-130 , 2019
Link:
https://doi.org/10.1109/IMICPW.2019.8933249
RT T1 <cTitle>2019 TEQIP III Sponsored International Conference on Microwave Integrated Circuits, Photonics and Wireless Networks (IMICPW)</cTitle>: T1 <Title>Performance Analysis of Underlap Double Gate Oxide Stacked Junctionless MOSFET for Analog and RF Applications</Title> UL https://suche.suub.uni-bremen.de/peid=ieee-8933249&Exemplar=1&LAN=DE A1 Bhattacharyya, Amit A1 Pachal, Prithviraj A1 Pradhan, Anirban A1 Chanda, Manash A1 De, Debashis YR 2019 K1 Logic gates K1 Capacitance K1 Mathematical model K1 High-k dielectric materials K1 MOSFET K1 Semiconductor process modeling K1 Transconductance K1 Underlap K1 high-k spacer K1 oxide stack K1 intrinsic capacitances K1 short-channel effect SP 126 OP 130 LK http://dx.doi.org/https://doi.org/10.1109/IMICPW.2019.8933249 DO https://doi.org/10.1109/IMICPW.2019.8933249 SF ELIB - SuUB Bremen
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