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1 Ergebnisse
1
Design of 6T SRAM Cell Using Optimized 20 nm SOI Junctionle..:
, In:
2019 IEEE Regional Symposium on Micro and Nanoelectronics (RSM)
,
Noor, Muhammad Faris Md
;
Alias, Nurul Ezaila
;
Hamzah, Afiq
.. - p. 141-144 , 2019
Link:
https://doi.org/10.1109/RSM46715.2019.8943541
RT T1
2019 IEEE Regional Symposium on Micro and Nanoelectronics (RSM)
: T1
Design of 6T SRAM Cell Using Optimized 20 nm SOI Junctionless Transistor
UL https://suche.suub.uni-bremen.de/peid=ieee-8943541&Exemplar=1&LAN=DE A1 Noor, Muhammad Faris Md A1 Alias, Nurul Ezaila A1 Hamzah, Afiq A1 Johari, Zaharah A1 Peng, Michael Tan Loong YR 2019 SN 2639-4642 K1 SRAM cells K1 Transistors K1 Stability criteria K1 SPICE K1 Logic gates K1 6T SRAM K1 RSNM K1 SCE K1 SPICE model K1 SOI-JLT K1 SNM K1 Taguchi SP 141 OP 144 LK http://dx.doi.org/https://doi.org/10.1109/RSM46715.2019.8943541 DO https://doi.org/10.1109/RSM46715.2019.8943541 SF ELIB - SuUB Bremen
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