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1 Ergebnisse
1
Detailed Fault Model for Physical Quantum Circuits:
, In:
2019 IEEE 28th Asian Test Symposium (ATS)
,
Deb, Arighna
;
Das, Debesh K.
- p. 153-1535 , 2019
Link:
https://doi.org/10.1109/ATS47505.2019.00028
RT T1 <cTitle>2019 IEEE 28th Asian Test Symposium (ATS)</cTitle>: T1 <Title>Detailed Fault Model for Physical Quantum Circuits</Title> UL https://suche.suub.uni-bremen.de/peid=ieee-8949400&Exemplar=1&LAN=DE A1 Deb, Arighna A1 Das, Debesh K. YR 2019 SN 2377-5386 K1 Logic gates K1 Circuit faults K1 Qubit K1 Integrated circuit modeling K1 Computational modeling K1 Fault model, reversible circuit, quantum circuit SP 153 OP 1535 LK http://dx.doi.org/https://doi.org/10.1109/ATS47505.2019.00028 DO https://doi.org/10.1109/ATS47505.2019.00028 SF ELIB - SuUB Bremen
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