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1 Ergebnisse
1
A Low-delay Configurable Register for FPGA:
, In:
2019 IEEE 13th International Conference on ASIC (ASICON)
,
Lu, Zhi-Yin
;
Liu, Jia-Feng
;
Pang, Yun-Bing
... - p. 1-4 , 2019
Link:
https://doi.org/10.1109/ASICON47005.2019.8983553
RT T1 <cTitle>2019 IEEE 13th International Conference on ASIC (ASICON)</cTitle>: T1 <Title>A Low-delay Configurable Register for FPGA</Title> UL https://suche.suub.uni-bremen.de/peid=ieee-8983553&Exemplar=1&LAN=DE A1 Lu, Zhi-Yin A1 Liu, Jia-Feng A1 Pang, Yun-Bing A1 Li, Zheug-Jie A1 Zhang, Yu-Fan A1 Lai, Jin-Mei A1 Wang, Jian YR 2019 SN 2162-755X K1 configurable register K1 FPGA K1 low delay SP 1 OP 4 LK http://dx.doi.org/https://doi.org/10.1109/ASICON47005.2019.8983553 DO https://doi.org/10.1109/ASICON47005.2019.8983553 SF ELIB - SuUB Bremen
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