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A Novel Ternary Half Adder & One Bit MultiplierCircuits bas..:
, In:
2018 International Conference on Intelligent Computing and Communication for Smart World (I2C2SW)
,
Gowri Sankar, P. A.
- p. 198-203 , 2018
Link:
https://doi.org/10.1109/I2C2SW45816.2018.8997120
RT T1 <cTitle>2018 International Conference on Intelligent Computing and Communication for Smart World (I2C2SW)</cTitle>: T1 <Title>A Novel Ternary Half Adder & One Bit MultiplierCircuits based on Emerging sub-32nm FET Technology</Title> UL https://suche.suub.uni-bremen.de/peid=ieee-8997120&Exemplar=1&LAN=DE A1 Gowri Sankar, P. A. YR 2018 K1 Logic gates K1 Adders K1 FinFETs K1 Multivalued logic K1 Delays K1 Threshold voltage K1 Double gate field effect transistor K1 FET K1 Graphene field effect transistor K1 MVL K1 Ternary Half Adder K1 Ternary Multiplier SP 198 OP 203 LK http://dx.doi.org/https://doi.org/10.1109/I2C2SW45816.2018.8997120 DO https://doi.org/10.1109/I2C2SW45816.2018.8997120 SF ELIB - SuUB Bremen
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