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1 Ergebnisse
1
Efficient Core Mapping on Customization of NoC Platforms:
, In:
2019 IEEE International Symposium on Smart Electronic Systems (iSES) (Formerly iNiS)
,
Kumar, Aruru Sai
;
Rao, T. V. K Hanumantha
- p. 57-62 , 2019
Link:
https://doi.org/10.1109/iSES47678.2019.00025
RT T1
2019 IEEE International Symposium on Smart Electronic Systems (iSES) (Formerly iNiS)
: T1
Efficient Core Mapping on Customization of NoC Platforms
UL https://suche.suub.uni-bremen.de/peid=ieee-9002466&Exemplar=1&LAN=DE A1 Kumar, Aruru Sai A1 Rao, T. V. K Hanumantha YR 2019 K1 Topology K1 Reliability K1 Delays K1 Benchmark testing K1 Task analysis K1 Linear programming K1 Network on Chip (NoC), core mapping, reliability, delay, area, power SP 57 OP 62 LK http://dx.doi.org/https://doi.org/10.1109/iSES47678.2019.00025 DO https://doi.org/10.1109/iSES47678.2019.00025 SF ELIB - SuUB Bremen
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