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1 Ergebnisse
1
A dual threshold voltage modified dynamic power cutoff tech..:
, In:
2019 IEEE International Conference on Electronics, Computing and Communication Technologies (CONECCT)
,
Nadella, Sai Dheeraj
;
Israel, Alan
;
Reddy, Gnaneswara
.. - p. 1-5 , 2019
Link:
https://doi.org/10.1109/CONECCT47791.2019.9012898
RT T1 <cTitle>2019 IEEE International Conference on Electronics, Computing and Communication Technologies (CONECCT)</cTitle>: T1 <Title>A dual threshold voltage modified dynamic power cutoff technique to consolidate leakage and speed in a VLSI subsystem</Title> UL https://suche.suub.uni-bremen.de/peid=ieee-9012898&Exemplar=1&LAN=DE A1 Nadella, Sai Dheeraj A1 Israel, Alan A1 Reddy, Gnaneswara A1 Rao, Nanditha A1 Rao, Madhav YR 2019 K1 Logic gates K1 Transistors K1 Microsoft Windows K1 Switching circuits K1 Delays K1 Leakage currents K1 low power circuit K1 leakage power K1 dual Vt technique K1 Power cutoff K1 multiplier SP 1 OP 5 LK http://dx.doi.org/https://doi.org/10.1109/CONECCT47791.2019.9012898 DO https://doi.org/10.1109/CONECCT47791.2019.9012898 SF ELIB - SuUB Bremen
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