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Optimized Design of 4H-SiC VDMOSFET for Low ON-resistance:
, In:
2019 16th China International Forum on Solid State Lighting & 2019 International Forum on Wide Bandgap Semiconductors China (SSLChina: IFWS)
,
Yin, Defu
;
Wu, Zhiming
;
Zou, Xian
... - p. 46-49 , 2019
Link:
https://doi.org/10.1109/SSLChinaIFWS49075.2019.9019763
RT T1 <cTitle>2019 16th China International Forum on Solid State Lighting & 2019 International Forum on Wide Bandgap Semiconductors China (SSLChina: IFWS)</cTitle>: T1 <Title>Optimized Design of 4H-SiC VDMOSFET for Low ON-resistance</Title> UL https://suche.suub.uni-bremen.de/peid=ieee-9019763&Exemplar=1&LAN=DE A1 Yin, Defu A1 Wu, Zhiming A1 Zou, Xian A1 Sun, Yongqiang A1 Wu, Yaping A1 Wang, Weiping A1 Li, Xu A1 Kang, Junyong YR 2019 K1 JFETs K1 Logic gates K1 Electric fields K1 Junctions K1 Performance evaluation K1 MOSFET K1 Breakdown voltage K1 Silicon Carbide K1 VDMOSFETs K1 Breakdown Voltage K1 ON-resistance K1 Figure of merit SP 46 OP 49 LK http://dx.doi.org/https://doi.org/10.1109/SSLChinaIFWS49075.2019.9019763 DO https://doi.org/10.1109/SSLChinaIFWS49075.2019.9019763 SF ELIB - SuUB Bremen
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