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1 Ergebnisse
1
The Simulated Annealing Based Logical Resynthesis Method fo..:
, In:
2020 IEEE Conference of Russian Young Researchers in Electrical and Electronic Engineering (EIConRus)
,
Vasilyev, Nikolay O.
;
Tiunov, Ivan V.
;
Ryzhova, Daria I.
- p. 1892-1894 , 2020
Link:
https://doi.org/10.1109/EIConRus49466.2020.9038959
RT T1 <cTitle>2020 IEEE Conference of Russian Young Researchers in Electrical and Electronic Engineering (EIConRus)</cTitle>: T1 <Title>The Simulated Annealing Based Logical Resynthesis Method for LUT-based FPGAs</Title> UL https://suche.suub.uni-bremen.de/peid=ieee-9038959&Exemplar=1&LAN=DE A1 Vasilyev, Nikolay O. A1 Tiunov, Ivan V. A1 Ryzhova, Daria I. YR 2020 SN 2376-6565 K1 FPGA K1 resynthesis K1 LUT SP 1892 OP 1894 LK http://dx.doi.org/https://doi.org/10.1109/EIConRus49466.2020.9038959 DO https://doi.org/10.1109/EIConRus49466.2020.9038959 SF ELIB - SuUB Bremen
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