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1
Lowering the Dark Count Rate of SPAD Implemented in CMOS FD..:
, In:
2019 Joint International EUROSOI Workshop and International Conference on Ultimate Integration on Silicon (EUROSOI-ULIS)
,
de Albuquerque, T. Chaves
;
Issartel, D.
;
Clerc, R.
... - p. 1-4 , 2019
Link:
https://doi.org/10.1109/EUROSOI-ULIS45800.2019.9041916
RT T1
2019 Joint International EUROSOI Workshop and International Conference on Ultimate Integration on Silicon (EUROSOI-ULIS)
: T1
Lowering the Dark Count Rate of SPAD Implemented in CMOS FDSOI Technology
UL https://suche.suub.uni-bremen.de/peid=ieee-9041916&Exemplar=1&LAN=DE A1 de Albuquerque, T. Chaves A1 Issartel, D. A1 Clerc, R. A1 Pittet, P. A1 Cellier, R. A1 Calmon, F. YR 2019 SN 2472-9132 K1 Single-photon avalanche diodes K1 Silicon-on-insulator K1 CMOS technology K1 Semiconductor process modeling K1 Implants K1 Junctions K1 Doping profiles K1 SPAD K1 CMOS FDSOI K1 DCR K1 TCAD simulation SP 1 OP 4 LK http://dx.doi.org/https://doi.org/10.1109/EUROSOI-ULIS45800.2019.9041916 DO https://doi.org/10.1109/EUROSOI-ULIS45800.2019.9041916 SF ELIB - SuUB Bremen
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