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1 Ergebnisse
1
Translation Validation of Code Generation from the SIGNAL D..:
, In:
2019 15th International Conference on Semantics, Knowledge and Grids (SKG)
,
Amjad, Hafiz Muhammad
;
Hu, Kai
;
Niu, Jianwei
... - p. 153-160 , 2019
Link:
https://doi.org/10.1109/SKG49510.2019.00034
RT T1 <cTitle>2019 15th International Conference on Semantics, Knowledge and Grids (SKG)</cTitle>: T1 <Title>Translation Validation of Code Generation from the SIGNAL Data-Flow Language to Verilog</Title> UL https://suche.suub.uni-bremen.de/peid=ieee-9044129&Exemplar=1&LAN=DE A1 Amjad, Hafiz Muhammad A1 Hu, Kai A1 Niu, Jianwei A1 Khan, Noor A1 Besnard, Loic A1 Talpin, Jean-Pierre YR 2019 K1 Hardware design languages K1 Mathematical model K1 Clocks K1 Semantics K1 Tools K1 Embedded systems K1 Encoding K1 translation validation, embedded systems, Verilog, SIGNAL, SIGALI, Yosys, semantics SP 153 OP 160 LK http://dx.doi.org/https://doi.org/10.1109/SKG49510.2019.00034 DO https://doi.org/10.1109/SKG49510.2019.00034 SF ELIB - SuUB Bremen
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