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1 Ergebnisse
1
Designing of AES Algorithm using Verilog:
, In:
2018 4th International Conference for Convergence in Technology (I2CT)
,
Soumya, V H
;
Neelagar, Mahesh B.
;
Kumaraswamy, K V
- p. 1-5 , 2018
Link:
https://doi.org/10.1109/I2CT42659.2018.9058322
RT T1
2018 4th International Conference for Convergence in Technology (I2CT)
: T1
Designing of AES Algorithm using Verilog
UL https://suche.suub.uni-bremen.de/peid=ieee-9058322&Exemplar=1&LAN=DE A1 Soumya, V H A1 Neelagar, Mahesh B. A1 Kumaraswamy, K V YR 2018 K1 Hardware design languages K1 Encryption K1 Signal processing algorithms K1 Clocks K1 Standards K1 Simulation K1 AES K1 Verilog K1 Xilinx ISE K1 plain text K1 cipher text SP 1 OP 5 LK http://dx.doi.org/https://doi.org/10.1109/I2CT42659.2018.9058322 DO https://doi.org/10.1109/I2CT42659.2018.9058322 SF ELIB - SuUB Bremen
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