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1 Ergebnisse
1
17.1 A −240dB-FoMjitter and −115dBc/Hz PN @ 100kHz, 7.7GHz ..:
, In:
2020 IEEE International Solid- State Circuits Conference - (ISSCC)
,
Lee, Yongsun
;
Seong, Taeho
;
Lee, Jeonghyun
... - p. 266-268 , 2020
Link:
https://doi.org/10.1109/ISSCC19947.2020.9062966
RT T1 <cTitle>2020 IEEE International Solid- State Circuits Conference - (ISSCC)</cTitle>: T1 <Title>17.1 A −240dB-FoMjitter and −115dBc/Hz PN @ 100kHz, 7.7GHz Ring-DCO-Based Digital PLL Using P/I-Gain Co-Optimization and Sequence-Rearranged Optimally Spaced TDC for Flicker-Noise Reduction</Title> UL https://suche.suub.uni-bremen.de/peid=ieee-9062966&Exemplar=1&LAN=DE A1 Lee, Yongsun A1 Seong, Taeho A1 Lee, Jeonghyun A1 Hwang, Chanwoong A1 Park, Hangi A1 Choi, Jaehyouk YR 2020 SN 2376-8606 K1 Jitter K1 Phase locked loops K1 Timing K1 Bandwidth K1 Optimization K1 Correlation K1 Phase noise SP 266 OP 268 LK http://dx.doi.org/https://doi.org/10.1109/ISSCC19947.2020.9062966 DO https://doi.org/10.1109/ISSCC19947.2020.9062966 SF ELIB - SuUB Bremen
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