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Verilog-A Modeling of Junction-less MOSFET in Sub- Threshol..:
, In:
2019 Women Institute of Technology Conference on Electrical and Computer Engineering (WITCON ECE)
,
Sen, Mitul
;
Gatait, Ardhendu
;
Ghosh, Sounak
... - p. 172-176 , 2019
Link:
https://doi.org/10.1109/WITCONECE48374.2019.9092930
RT T1
2019 Women Institute of Technology Conference on Electrical and Computer Engineering (WITCON ECE)
: T1
Verilog-A Modeling of Junction-less MOSFET in Sub- Threshold Regime for Ultra Low-Power Application
UL https://suche.suub.uni-bremen.de/peid=ieee-9092930&Exemplar=1&LAN=DE A1 Sen, Mitul A1 Gatait, Ardhendu A1 Ghosh, Sounak A1 Chanda, Manash A1 Roy, Swarnil A1 Debnath, Papiya YR 2019 K1 MOSFET K1 Semiconductor device modeling K1 Logic gates K1 Integrated circuit modeling K1 Delays K1 Hardware design languages K1 Data models K1 Verilog A K1 Double gate Junctionless MOSFET K1 Power K1 Delay K1 CMOS SP 172 OP 176 LK http://dx.doi.org/https://doi.org/10.1109/WITCONECE48374.2019.9092930 DO https://doi.org/10.1109/WITCONECE48374.2019.9092930 SF ELIB - SuUB Bremen
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