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A dynamic hardware redundancy mechanism for the in-field fa..:
, In:
2020 23rd International Symposium on Design and Diagnostics of Electronic Circuits & Systems (DDECS)
,
Rodriguez Condia, Josie E.
;
Narducci, Pierpaolo
;
Reorda, M. Sonza
. - p. 1-6 , 2020
Link:
https://doi.org/10.1109/DDECS50862.2020.9095665
RT T1
2020 23rd International Symposium on Design and Diagnostics of Electronic Circuits & Systems (DDECS)
: T1
A dynamic hardware redundancy mechanism for the in-field fault detection in cores of GPGPUs
UL https://suche.suub.uni-bremen.de/peid=ieee-9095665&Exemplar=1&LAN=DE A1 Rodriguez Condia, Josie E. A1 Narducci, Pierpaolo A1 Reorda, M. Sonza A1 Sterpone, L. YR 2020 SN 2473-2117 K1 Fault detection K1 Hardware K1 Redundancy K1 Graphics processing units K1 Degradation K1 Monitoring K1 Duplication with Comparison (DWC) K1 General Purpose Graphics Processing Units (GPGPUs) K1 Graphics Processors SP 1 OP 6 LK http://dx.doi.org/https://doi.org/10.1109/DDECS50862.2020.9095665 DO https://doi.org/10.1109/DDECS50862.2020.9095665 SF ELIB - SuUB Bremen
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