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FPGA-Based Acceleration of LU decomposition for Analog and ..:
, In:
2020 33rd International Conference on VLSI Design and 2020 19th International Conference on Embedded Systems (VLSID)
,
Mahajan, Yogesh
;
Obla, Shashank
;
Namboothiripad, Mini K.
... - p. 131-136 , 2020
Link:
https://doi.org/10.1109/VLSID49098.2020.00040
RT T1 <cTitle>2020 33rd International Conference on VLSI Design and 2020 19th International Conference on Embedded Systems (VLSID)</cTitle>: T1 <Title>FPGA-Based Acceleration of LU decomposition for Analog and RF Circuit Simulation</Title> UL https://suche.suub.uni-bremen.de/peid=ieee-9105410&Exemplar=1&LAN=DE A1 Mahajan, Yogesh A1 Obla, Shashank A1 Namboothiripad, Mini K. A1 Datar, Mandar J. A1 Sharma, Niraj N. A1 Patkar, Sachin B. YR 2020 SN 2380-6923 K1 FPGA K1 Harmonic Balance Method K1 RF Circuit Simulation K1 Sparse LU Decomposition K1 Vivado SP 131 OP 136 LK http://dx.doi.org/https://doi.org/10.1109/VLSID49098.2020.00040 DO https://doi.org/10.1109/VLSID49098.2020.00040 SF ELIB - SuUB Bremen
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