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PowerPlanningDL: Reliability-Aware Framework for On-Chip Po..:
, In:
2020 Design, Automation & Test in Europe Conference & Exhibition (DATE)
,
Dey, Sukanta
;
Nandi, Sukumar
;
Trivedi, Gaurav
- p. 1520-1525 , 2020
Link:
https://doi.org/10.23919/DATE48585.2020.9116536
RT T1 <cTitle>2020 Design, Automation & Test in Europe Conference & Exhibition (DATE)</cTitle>: T1 <Title>PowerPlanningDL: Reliability-Aware Framework for On-Chip Power Grid Design using Deep Learning</Title> UL https://suche.suub.uni-bremen.de/peid=ieee-9116536&Exemplar=1&LAN=DE A1 Dey, Sukanta A1 Nandi, Sukumar A1 Trivedi, Gaurav YR 2020 SN 1558-1101 K1 Power grids K1 Deep learning K1 Planning K1 Training K1 Neural networks K1 Reliability engineering K1 Deep Learning K1 Electromigration K1 IR drop K1 Neural Networks K1 Power Grid Network K1 Reliability K1 VLSI SP 1520 OP 1525 LK http://dx.doi.org/https://doi.org/10.23919/DATE48585.2020.9116536 DO https://doi.org/10.23919/DATE48585.2020.9116536 SF ELIB - SuUB Bremen
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