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1
A Low DelayArchitecture for Logarithmic Multiplication:
, In:
2020 4th International Conference on Trends in Electronics and Informatics (ICOEI)(48184)
,
Kssrb, Pavan Kumar
;
N, Sai Shantan
;
S, Pravallika
.. - p. 70-74 , 2020
Link:
https://doi.org/10.1109/ICOEI48184.2020.9143034
RT T1 <cTitle>2020 4th International Conference on Trends in Electronics and Informatics (ICOEI)(48184)</cTitle>: T1 <Title>A Low DelayArchitecture for Logarithmic Multiplication</Title> UL https://suche.suub.uni-bremen.de/peid=ieee-9143034&Exemplar=1&LAN=DE A1 Kssrb, Pavan Kumar A1 N, Sai Shantan A1 S, Pravallika A1 V, BhaskaraRaju A1 R, Ramesh S YR 2020 K1 Delays K1 Adders K1 Multiplexing K1 Detectors K1 Conferences K1 Market research K1 Informatics K1 Digital Signal Processing K1 logarithmic number system K1 Mitchell's algorithm K1 Operand Decomposition K1 Improved Operand Decomposition SP 70 OP 74 LK http://dx.doi.org/https://doi.org/10.1109/ICOEI48184.2020.9143034 DO https://doi.org/10.1109/ICOEI48184.2020.9143034 SF ELIB - SuUB Bremen
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