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1 Ergebnisse
1
Improving HLS Generated Accelerators Through Relaxed Memory..:
, In:
2020 IEEE International Parallel and Distributed Processing Symposium Workshops (IPDPSW)
,
Rohde, Johanna
;
Muller, Karsten
;
Hochberger, Christian
- p. 74-81 , 2020
Link:
https://doi.org/10.1109/IPDPSW50202.2020.00020
RT T1
2020 IEEE International Parallel and Distributed Processing Symposium Workshops (IPDPSW)
: T1
Improving HLS Generated Accelerators Through Relaxed Memory Access Scheduling
UL https://suche.suub.uni-bremen.de/peid=ieee-9150344&Exemplar=1&LAN=DE A1 Rohde, Johanna A1 Muller, Karsten A1 Hochberger, Christian YR 2020 K1 Tools K1 Hardware K1 Runtime K1 Kernel K1 Benchmark testing K1 Schedules K1 Pipeline processing K1 High-Level-Synthesis K1 Memory Dependences K1 FPGA K1 Memory Disambiguation K1 Write Squashing K1 Bypassing SP 74 OP 81 LK http://dx.doi.org/https://doi.org/10.1109/IPDPSW50202.2020.00020 DO https://doi.org/10.1109/IPDPSW50202.2020.00020 SF ELIB - SuUB Bremen
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