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1
Representing Gate-Level SET Faults by Multiple SEU Faults a..:
, In:
2020 IEEE 26th International Symposium on On-Line Testing and Robust System Design (IOLTS)
,
Bagbaba, Ahmet Cagri
;
Jenihhin, Maksim
;
Ubar, Raimund
. - p. 1-6 , 2020
Link:
https://doi.org/10.1109/IOLTS50870.2020.9159715
RT T1
2020 IEEE 26th International Symposium on On-Line Testing and Robust System Design (IOLTS)
: T1
Representing Gate-Level SET Faults by Multiple SEU Faults at RTL
UL https://suche.suub.uni-bremen.de/peid=ieee-9159715&Exemplar=1&LAN=DE A1 Bagbaba, Ahmet Cagri A1 Jenihhin, Maksim A1 Ubar, Raimund A1 Sauer, Christian YR 2020 SN 1942-9401 K1 Circuit faults K1 Logic gates K1 Safety K1 Integrated circuit modeling K1 Tools K1 Security K1 Semiconductor lasers K1 SET K1 SEU K1 multiple faults K1 functional safety K1 hardware security K1 fault injection SP 1 OP 6 LK http://dx.doi.org/https://doi.org/10.1109/IOLTS50870.2020.9159715 DO https://doi.org/10.1109/IOLTS50870.2020.9159715 SF ELIB - SuUB Bremen
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