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1 Ergebnisse
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Evaluation of Non-Series-Parallel Structures for BTI-Aware ..:
, In:
2020 IEEE International Symposium on Circuits and Systems (ISCAS)
,
Kessler, Henrique
;
Finkenauer, Plinio
;
Both, Thiago H.
.. - p. 1-5 , 2020
Link:
https://doi.org/10.1109/ISCAS45731.2020.9180594
RT T1
2020 IEEE International Symposium on Circuits and Systems (ISCAS)
: T1
Evaluation of Non-Series-Parallel Structures for BTI-Aware Automated Design Methodologies
UL https://suche.suub.uni-bremen.de/peid=ieee-9180594&Exemplar=1&LAN=DE A1 Kessler, Henrique A1 Finkenauer, Plinio A1 Both, Thiago H. A1 da Rosa, Leomar A1 Camargo, Vinicius V. YR 2020 SN 2158-1525 K1 Logic gates K1 Transistors K1 Delays K1 Topology K1 Stress K1 Mathematical model K1 Standards K1 complex gates K1 EDA K1 BTI K1 reliability K1 aging SP 1 OP 5 LK http://dx.doi.org/https://doi.org/10.1109/ISCAS45731.2020.9180594 DO https://doi.org/10.1109/ISCAS45731.2020.9180594 SF ELIB - SuUB Bremen
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