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1 Ergebnisse
1
DRAB-LOCUS: An Area-Efficient AES Architecture for Hardware..:
, In:
2020 IEEE International Symposium on Circuits and Systems (ISCAS)
,
Grycel, Jacob T.
;
Walls, Robert J.
- p. 1-5 , 2020
Link:
https://doi.org/10.1109/ISCAS45731.2020.9181186
RT T1
2020 IEEE International Symposium on Circuits and Systems (ISCAS)
: T1
DRAB-LOCUS: An Area-Efficient AES Architecture for Hardware Accelerator Co-Location on FPGAs
UL https://suche.suub.uni-bremen.de/peid=ieee-9181186&Exemplar=1&LAN=DE A1 Grycel, Jacob T. A1 Walls, Robert J. YR 2020 SN 2158-1525 K1 Field programmable gate arrays K1 Encryption K1 Registers K1 Schedules K1 Throughput K1 Table lookup K1 Digital signal processing SP 1 OP 5 LK http://dx.doi.org/https://doi.org/10.1109/ISCAS45731.2020.9181186 DO https://doi.org/10.1109/ISCAS45731.2020.9181186 SF ELIB - SuUB Bremen
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