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1 Ergebnisse
1
Electrical Masking Improvement with Standard Logic Cell Syn..:
, In:
2020 IEEE 63rd International Midwest Symposium on Circuits and Systems (MWSCAS)
,
Olowogemo, Semiu A.
;
Yiwere, Ahmed
;
Lin, Bor-Tyng
... - p. 619-622 , 2020
Link:
https://doi.org/10.1109/MWSCAS48704.2020.9184651
RT T1 <cTitle>2020 IEEE 63rd International Midwest Symposium on Circuits and Systems (MWSCAS)</cTitle>: T1 <Title>Electrical Masking Improvement with Standard Logic Cell Synthesis Using 45 nm Technology Node</Title> UL https://suche.suub.uni-bremen.de/peid=ieee-9184651&Exemplar=1&LAN=DE A1 Olowogemo, Semiu A. A1 Yiwere, Ahmed A1 Lin, Bor-Tyng A1 Qiu, Hao A1 Robinson, William H. A1 Limbrick, Daniel B. YR 2020 SN 1558-3899 K1 Logic gates K1 Transient analysis K1 Integrated circuit modeling K1 Low voltage K1 Robustness K1 Circuit faults K1 vulnerable gates K1 vulnerable paths K1 pulse propagation K1 electrical masking K1 single-event transient (SET) pulse K1 HSPICE K1 PVT variation K1 mitigation SP 619 OP 622 LK http://dx.doi.org/https://doi.org/10.1109/MWSCAS48704.2020.9184651 DO https://doi.org/10.1109/MWSCAS48704.2020.9184651 SF ELIB - SuUB Bremen
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