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1 Ergebnisse
1
Fault-Tolerance Mechanism Analysis on NVDLA-Based Design Us..:
, In:
2020 International Symposium on VLSI Design, Automation and Test (VLSI-DAT)
,
Liu, Shu-Ming
;
Tang, Luba
;
Huang, Ning-Chi
... - p. 1-3 , 2020
Link:
https://doi.org/10.1109/VLSI-DAT49148.2020.9196335
RT T1
2020 International Symposium on VLSI Design, Automation and Test (VLSI-DAT)
: T1
Fault-Tolerance Mechanism Analysis on NVDLA-Based Design Using Open Neural Network Compiler and Quantization Calibrator
UL https://suche.suub.uni-bremen.de/peid=ieee-9196335&Exemplar=1&LAN=DE A1 Liu, Shu-Ming A1 Tang, Luba A1 Huang, Ning-Chi A1 Tsai, Der-Yu A1 Yang, Ming-Xue A1 Wu, Kai-Chiang YR 2020 SN 2472-9124 K1 Circuit faults K1 Quantization (signal) K1 Machine learning K1 Random access memory K1 Neural networks K1 Load modeling K1 Deep learning accelerators K1 Compilers K1 NVDLA K1 ONNC K1 fault tolerant SP 1 OP 3 LK http://dx.doi.org/https://doi.org/10.1109/VLSI-DAT49148.2020.9196335 DO https://doi.org/10.1109/VLSI-DAT49148.2020.9196335 SF ELIB - SuUB Bremen
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