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Experiments and optimizations for TVM on RISC-V Architectur..:
, In:
2020 International Symposium on VLSI Design, Automation and Test (VLSI-DAT)
,
Chen, Yi-Ru
;
Liao, Hui-Hsin
;
Chang, Chia-Hsuan
... - p. 1-4 , 2020
Link:
https://doi.org/10.1109/VLSI-DAT49148.2020.9196477
RT T1
2020 International Symposium on VLSI Design, Automation and Test (VLSI-DAT)
: T1
Experiments and optimizations for TVM on RISC-V Architectures with P Extension
UL https://suche.suub.uni-bremen.de/peid=ieee-9196477&Exemplar=1&LAN=DE A1 Chen, Yi-Ru A1 Liao, Hui-Hsin A1 Chang, Chia-Hsuan A1 Lin, Che-Chia A1 Lee, Chao-Lin A1 Chang, Yuan-Ming A1 Yang, Chun-Chieh A1 Lee, Jenq-Kuen YR 2020 SN 2472-9124 K1 Runtime K1 Convolution K1 Optimization K1 Machine learning K1 Computational modeling K1 Schedules K1 Registers SP 1 OP 4 LK http://dx.doi.org/https://doi.org/10.1109/VLSI-DAT49148.2020.9196477 DO https://doi.org/10.1109/VLSI-DAT49148.2020.9196477 SF ELIB - SuUB Bremen
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