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1 Ergebnisse
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Performance Evaluation of Logic Circuits with 2D Negative-C..:
, In:
2020 International Symposium on VLSI Technology, Systems and Applications (VLSI-TSA)
,
Lin, Chia-Chen
;
Wu, Yi-Jui
;
You, Wei-Xiang
. - p. 62-63 , 2020
Link:
https://doi.org/10.1109/VLSI-TSA48913.2020.9203647
RT T1
2020 International Symposium on VLSI Technology, Systems and Applications (VLSI-TSA)
: T1
Performance Evaluation of Logic Circuits with 2D Negative-Capacitance FETs Considering the Impact of Spacers
UL https://suche.suub.uni-bremen.de/peid=ieee-9203647&Exemplar=1&LAN=DE A1 Lin, Chia-Chen A1 Wu, Yi-Jui A1 You, Wei-Xiang A1 Su, Pin YR 2020 K1 Two dimensional displays K1 Capacitance K1 Logic gates K1 Delays K1 High-k dielectric materials K1 Field effect transistors K1 Circuit optimization SP 62 OP 63 LK http://dx.doi.org/https://doi.org/10.1109/VLSI-TSA48913.2020.9203647 DO https://doi.org/10.1109/VLSI-TSA48913.2020.9203647 SF ELIB - SuUB Bremen
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